ARM AMBA NIC-301 Spezifikationen PDF herunterladen (Seite 94)

Programmers Model

ID062813 Non-Confidential

Figure 3-20 Test chip CFGREG42 Register bit assignments

Table 3-22 shows the bit assignments.

31 16 15 8 0

0 11000 1 1110000000000 0011 111111

Reserved

L2RSTDISABLE

30 29 28 27 26 25 24 23 22 21 10 9 6 43

BROADCASTCACHEMAINT

Reserved

ACP_BARE_METAL

ACP_AWUSER[5:0]

AINACTS

SYSBARDISABLE

ACP_64N128

ACP_ADDRTRANS

ACP_ARUSER[5:0]

ACP_AUSER_OVERRIDE

ACINACTM

BROADCASTOUTER

BROADCASTINNER

CP15SDISABLE[1:0]

Reserved

CFGEND[1:0]

Reserved

Table 3-22 Test chip CFGREG42 Register bit assignments

Bits Name Function

[31] - Reserved. Do not modify.

[30] L2RSTDISABLE Disables automatic L2 cache invalidate at reset:

Hardware resets L2 valid RAM contents.

Hardware does not reset valid RAM contents.

The default is

[29] BROADCASTCACHEMAINT Enables broadcasting of cache maintenance operations to downstream caches:

Disables broadcasting of cache maintenance operations to downstream

caches.

Enables broadcasting of cache maintenance operations to downstream

caches.

The default is

[28] BROADCASTOUTER Enables broadcasting of outer shareable transactions:

Disables external broadcast of outer shareable transactions.

Enables external broadcast of outer shareable transactions.

The default is

[27] BROADCASTINNER Enables broadcasting on inner shareable transactions:

Disables broadcasting of inner shareable transactions.

Enables broadcasting of inner shareable transactions.

The default is

[26] SYSBARDISABLE Disables broadcasting barriers onto system bus:

Enables broadcast barriers onto the system bus. This requires an

AMBA4 interconnect.

Disables broadcast barriers onto the system bus. This is compatible with

an AXI3 interconnect.

The default is

[25] - Reserved. Do not modify.

1 2 ... 89 90 91 92 93 94 95 96 97 98 99 ... 177 178

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