ARM AMBA NIC-301 Spezifikationen PDF herunterladen (Seite 126)

Programmers Model

ID062813 Non-Confidential

Configurations Not applicable.

Attributes See Table 3-43 on page 3-62.

Figure 3-40 shows the bit assignments.

Figure 3-40 System counter COMPID3 Control Register bit assignments

Table 3-55 shows the bit assignments.

System counter read register summary

The system counter read registers base address is

0x2A80_0000

. Table 3-56 shows the system

counter read registers and their offsets from the system counter read register base memory

address.

31 0

0 00000 0 000001011000 0000 000000 01

COMPID3

Table 3-55 System counter COMPID3 Control Register bit assignments

Bits Name Function

[31:0] COMPID3 System counter component identification control register 3.

The default is

0x0000_00B1

Table 3-56 System counter read register summary

Offset Name Type Test chip reset Width Description

0x00 - 0x04

--- -Reserved.

Do not write to or read from these registers.

0x08

CNTCVL RO

0x0000_0000

32 System counter lower 32 bits read register.

See CNTCVL on page 3-70.

0x0C

CNTCVU RO

0x0000_0000

32 System counter upper 32 bits read register.

See CNTCVU on page 3-70.

0x10

CNTFID0 RO

0x0000_0000

32 Base frequency ID read register.

See CNTFID0 on page 3-71.

0xFDC

0x14

--- -Reserved.

Do not write to or read from these registers.

0xFE0

PID0 RO

0x0000_0099

32 System counter Peripheral Identification read register 0.

See PID0 on page 3-71.

0xFE4

PID1 RO

0x0000_0010

32 System counter Peripheral Identification read register 1.

See PID1 on page 3-72.

0xFE8

PID2 RO

0x0000_0004

32 System counter Peripheral Identification read register 2.

See PID2 on page 3-72.

0xFEC

PID3 RO

0x0000_0000

32 System counter Peripheral Identification read register 3.

See PID3 on page 3-73.

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