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Programmers Model
ARM DDI 0503F Copyright © 2012-2013 ARM. All rights reserved. 3-5
ID062813 Non-Confidential
Table 3-1 shows the daughterboard peripheral interfaces.
3.2.2 Remapping memory
This section describes the remap options for address
0x00_0000_0000
. It contains the following
subsections:
• SMC or AXI
• Chip-select Remap on page 3-6
• Chip-select Remap on page 3-6.
SMC or AXI
SCC register bits CFGREG4[1:0] control whether AXI or SMC is mapped to the lower 512MB
of memory. This enables booting from external AXI. One SMC option also selects external AXI
enabled, and the other SMC option selects external AXI disabled. See Test chip SCC Register 4
on page 3-19.
Table 3-1 Daughterboard memory map
Address range Size Description
0x00_0000_0000 - 0x00_03FF_FFFF
64MB CS0-Motherboard NOR flash 0:
• Also accessible at
0x00_0800_0000
.
0x00_0400_0000 - 0x00_07FF_FFFF
64MB Secure RAM
0x00_0800_0000 - 0x00_0BFF_FFFF
64MB CS0-Motherboard NOR flash 0:
• Also accessible at
0x00_0000_0000
.
0x00_0C00_0000 - 0x00_0FFF_FFFF
64MB CS4-Motherboard NOR flash 1
0x00_1000_0000 - 0x00_13FF_FFFF
64MB CS5-Reserved
0x00_1400_0000 - 0x00_17FF_FFFF
64MB CS1-Pseudostatic RAM, PSRAM, on the motherboard
0x00_1800_0000 - 0x00_1BFF_FFFF
64MB CS2-Video/ETH/USB on the motherboard
0x00_1C00_0000 - 0x00_1FFF_FFFF
64MB CS3-system registers and peripherals on the motherboard
0x00_0000_0000 - 0x00_1FFF_FFFF
512MB External AXI master interface, remap option
0x00_2000_0000 - 0x00_2FFF_FFFF
256MB Test chip peripherals
0x00_3000_0000 - 0x00_3FFF_FFFF
256MB Cortex-A15 Accelerator Coherency Port (ACP)
0x00_4000_0000 - 0x00_7FFF_FFFF
1GB External AXI between daughterboards
0x00_8000_0000 - 0x00_FFFF_FFFF
2GB CoreTile Express A15×2 A7×3 daughterboard DDR2, block 1
0x01_0000_0000 - 0x07_FFFF_FFFF
28GB Reserved
0x08_0000_0000 - 0x08_7FFF_FFFF
2GB CoreTile Express A15×2 A7×3 daughterboard DDR2, alias to block 1
0x08_8000_0000 - 0x08_FFFF_FFFF
2GB CoreTile Express A15×2 A7×3 daughterboard DDR2, alias to block 1
0x09_0000_0000 - 0x7F_FFFF_FFFF
476GB Reserved
0x80_0000_0000 - 0x80_7FFF_FFFF
2GB CoreTile Express A15×2 A7×3 daughterboard DDR2, alias to block 1
0x80_8000_0000 - 0x80_FFFF_FFFF
2GB CoreTile Express A15×2 A7×3 daughterboard DDR2, alias to block 1
0x81_0000_0000 - 0xFF_FFFF_FFFF
508GB Reserved
- CoreTile 1
- Express A15×2 A7×3 1
- CoreTile Express A15×2 A7×3 2
- CE Declaration of Conformity 3
- Contents 4
- Appendix B HDLCD controller 5
- Appendix D Revisions 5
- • About this book on page vii 6
- • Feedback on page xi 6
- About this book 7
- Preface 10
- ID062813 Non-Confidential 10
- Feedback 11
- Chapter 1 12
- Introduction 12
- 1.2 Precautions 15
- Chapter 2 16
- Hardware Description 16
- MBM_nRST 29
- Internal resets 32
- 0x0000_0000 38
- 2.7 Clocks 39
- (CLKF + 1) 46
- (CLKOD + 1) (CLKR + 1)x 46
- 2.8 Interrupts 49
- 2.8.2 Interrupts 50
- 2.9 HDLCD 53
- 2.10 DDR2 memory interface 54
- 2.11 Debug 55
- Components Technical 56
- Reference Manual 56
- Chapter 3 58
- UNPREDICTABLE behavior 59
- 3.2 Daughterboard memory map 60
- You can access NOR 0 at 61
- and at 61
- 0x00_0000_0000 62
- 3.3 Test chip SCC registers 69
- SMC_ADDR_MATCH1_0 75
- SMC_ADDR_MASK1_0 75
- DMA_BOOT_ADDR 79
- DAP ROM Default Target ID 82
- DAP ROM Default Instance ID 83
- A15_CRNTCLK[3:0] 88
- A7_CRNTCLK[3:0] 88
- 31 16 15 8 0 92
- Programmers Model 100
- 0x000A50F5 to the 108
- Cortex-A15_A7 CPU ID 110
- 0x2A43_0000 119
- Reserved 120
- 0x2A80_0000 126
- CNTPL0ACR 136
- CNTP_TVAL 139
- CNTVL_CVAL 140
- Appendix A 147
- Signal Descriptions 147
- HDRXHDRY 148
- TRACE (DUAL) TRACE (SINGLE) 148
- Figure A-2 HSB multiplexing 149
- A.3 Header connectors 151
- Appendix B 155
- HDLCD controller 155
- B.1 Introduction 156
- B.2 HDLCD Programmers Model 157
- 31 16 15 8 7 0 158
- FB_BASE_ADDR 163
- FB_LINE_COUNT 164
- RESERVED 164
- FB_LINE_PITCH 165
- 31 12 11 0 167
- Reserved V_SYNC 167
- Reserved V_BACK_PORCH 167
- Reserved V_DATA 168
- Reserved V_FRONT_PORCH 168
- Reserved H_SYNC 169
- Reserved H_BACK_PORCH 169
- Reserved H_DATA 170
- Reserved H_FRONT_PORCH 170
- 31 30 5432 0 173
- BIG_ENDIAN 173
- BYTES_PER_PIXEL 173
- Appendix C 175
- Electrical Specifications 175
- C.1 AC characteristics 176
- Appendix D 177
- Revisions 177
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