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Glossary
ARM DDI 0337I Copyright © 2005-2008, 2010 ARM Limited. All rights reserved. Glossary-5
ID072410 Non-Confidential
Embedded Trace Macrocell (ETM)
A hardware macrocell that, when connected to a processor core, outputs instruction trace
information on a trace port.
Endianness The scheme that determines the order of successive bytes of a data word when it is stored in
memory.
See also Little-endian and Big-endian
ETB See Embedded Trace Buffer.
ETM See Embedded Trace Macrocell.
Exception An error or event which can cause the processor to suspend the currently executing instruction
stream and execute a specific exception handler or interrupt service routine. The exception could
be an external interrupt or NMI, or it could be a fault or error event that is considered serious
enough to require that program execution is interrupted. Examples include attempting to
perform an invalid memory access, external interrupts, and undefined instructions. When an
exception occurs, normal program flow is interrupted and execution is resumed at the
corresponding exception vector. This contains the first instruction of the interrupt service
routine to deal with the exception.
Exception handler
See Interrupt service routine.
Exception vector See Interrupt vector.
External PPB PPB memory space at
0xE0040000
to
0xE00FFFFF
.
Flash Patch and Breakpoint unit (FPB)
A set of address matching tags, that reroute accesses into flash to a special part of SRAM. This
permits patching flash locations for breakpointing and quick fixes or changes.
Formatter The formatter is an internal input block in the ETB and TPIU that embeds the trace source ID
within the data to create a single trace stream.
Halfword A 16-bit data item.
Halt mode One of two mutually exclusive debug modes. In halt mode all processor execution halts when a
breakpoint or watchpoint is encountered. All processor state, coprocessor state, memory and
input/output locations can be examined and altered by the JTAG interface.
See also Monitor debug-mode.
Host A computer that provides data and other services to another computer. Especially, a computer
providing debugging services to a target being debugged.
HTM See AHB Trace Macrocell.
ICode Memory Memory space at
0x00000000
to
0x1FFFFFFF
.
Illegal instruction An instruction that is architecturally Undefined.
Implementation-defined
The behavior is not architecturally defined, but is defined and documented by individual
implementations.
Implementation-specific
The behavior is not architecturally defined, and does not have to be documented by individual
implementations. Used when there are a number of implementation options available and the
option chosen does not affect software compatibility.
- Technical Reference Manual 1
- Cortex-M3 2
- Contents 3
- List of Tables 5
- List of Figures 7
- • About this book on page x 9
- • Feedback on page xiii 9
- About this book 10
- Preface 11
- Other publications 12
- Feedback 13
- Chapter 1 14
- Introduction 14
- 1.1 About the processor 15
- 1.2 Features 16
- 1.3 Interfaces 17
- 1.4 Configurable options 18
- 1.5 Product documentation 19
- 1.6 Product revisions 22
- 0xE000ED14 23
- Chapter 2 25
- Functional Description 25
- 2.1 About the functions 26
- 2.2 Interfaces 28
- Chapter 3 31
- Programmers Model 31
- 3.3 Instruction set summary 34
- — STKALIGN bit to 1 40
- — UNALIGN_TRP bit to 1 40
- 3.4 System address map 41
- LDRH, STR, STRH 42
- 3.5 Write buffer 44
- 3.6 Exclusive monitor 45
- 3.7 Bit-banding 46
- Figure 3-2 Bit-band mapping 47
- 3.9 Exceptions 50
- Chapter 4 52
- System Control 52
- 4.1 About system control 53
- 4.2 Register summary 54
- 4.3 Register descriptions 56
- Chapter 5 58
- Memory Protection Unit 58
- 5.1 About the MPU 59
- 5.3 MPU programmers model 61
- Chapter 6 62
- 6.1 About the NVIC 63
- 6.3 NVIC programmers model 65
- Chapter 7 67
- 7.1 About debug 68
- 0xE000ED00 69
- 0xE00FF000 70
- 7.2 About the AHB-AP 72
- 7.3.2 FPB programmers model 76
- Chapter 8 77
- 8.1 About the DWT 78
- 8.3 DWT Programmers Model 80
- 0x40000000 81
- 0x4F000000 81
- 0x10000000 81
- 0x1F000000 81
- Chapter 9 82
- 9.1 About the ITM 83
- 9.3 ITM programmers model 85
- PRIVMASK 86
- Chapter 10 87
- 10.1 About the ETM 88
- Figure 10-1 ETM block diagram 89
- 10.2.9 Operation 94
- 10.3 ETM Programmers model 95
- Embedded Trace Macrocell 100
- ID072410 Non-Confidential 100
- Reserved 102
- 26 25 24 102
- Trace control enable 102
- Reserved, RAZ 106
- ETM powered up 106
- TRIGGER output value 107
- Chapter 11 109
- Trace Port Interface Unit 109
- 11.1 About the Cortex-M3 TPIU 110
- 11.3 TPIU programmers model 113
- TRIGGER input value 116
- Appendix A 122
- Revisions 122
- Glossary 129
- 0x00000000 132
- 0x1FFFFFFFF 132
- 0xE0040000 133
- 0xE00FFFFF 133
- 0x1FFFFFFF 133
- 0xE0000000 134
- 0xE003FFFF 134
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