
6
Confidential
111111
Introduction to
Instruction Sets
121212
ARM Instruction Set
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All instructions are 32 bits long / many execute in a single cycle
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Instructions are conditionally executed
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A load / store architecture
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Example data processing instructions
SUB r0,r1,#5
ADD r2,r3,r3,LSL #2
ADDEQ r5,r5,r6
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Example branching instruction
B <Label>
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Example memory access instructions
LDR r0,[r1]
STRNEB r2,[r3,r4]
STMFD sp!,{r4-r8,lr}
r0 = r1 - 5
r2 = r3 + (r3 * 4)
IF EQ condition true r5 = r5 + r6
Branch forwards or backwards relative to
current PC (+/- 32MB range)
Load word at address r1 into r0
IF NE condition true, store bottom byte
of r2 to address r3+r4
Store registers r4 to r8 and lr on
stack. Then update stack pointer
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