ARM Cortex-M3 Bedienungsanleitung Seite 23

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Multiple sleep modes supported
Controlled by NVIC
Sleep Now
Wait for Interrupt/Event instructions
Sleep On Exit
Sleep immediately on return from last ISR
Deep Sleep
Long duration sleep, so PLL can be stopped
Exports additional output signal SLEEPDEEP
Cortex
-
M3 system is clock gated in all sleep modes
Sleep signal is exported allowing external system to be clock gated also
NVIC interrupt Interface stays awake
Wake
-
Up Interrupt Controller (WIC)
External wake
-
up detector allows Cortex
-
M3 to be fully powered down
Effective with State
-
Retention / Power Gating (SRPG) methodology
Power Management
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