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Memory Interface

3.3 Bus cycle types

The ARM7TDMI processor bus interface is pipelined. This gives the maximum time for

a memory cycle to decode the address and respond to the access request:

• memory request signals are broadcast in the bus cycle ahead of the bus cycle to

which they refer

• address class signals are broadcast half a clock cycle ahead of the bus cycle to

which they refer.

A single memory cycle is shown in Figure 3-1.

Figure 3-1 Simple memory cycle

The ARM7TDMI processor bus interface can perform four different types of bus cycle:

• a nonsequential cycle requests a transfer to or from an address which is unrelated

to the address used in the preceding cycle

• a sequential cycle requests a transfer to or from an address which is either the

same, one word, or one halfword greater than the address used in the preceding

cycle

• an internal cycle does not require a transfer because it is performing an internal

function, and no useful prefetching can be performed at the same time

• a coprocessor register transfer cycle uses the data bus to communicate with a

coprocessor, but does not require any action by the memory system.

MCLK

A[31:0]

D[31:0]

APE

nMREQ

SEQ

1 2 ... 69 70 71 72 73 74 75 76 77 78 79 ... 283 284

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ARM ARM7TDMI Bedienungsanleitung Seite 74