ARM IM-AD1 Betriebsanweisung PDF herunterladen (Seite 26)

Hardware Reference

3.1 Differences in signal routing between supported logic modules

The Integrator/LM-XCV600E+ and LM-EP20K600E+ logic module types route the

signals from the interface module differently as follows:

The

• LM-XCV600E+ is fitted with a Xilinx FPGA and routes the interface module

ABANK[59:0] signals to bank 0 on the FPGA and the BBANK[53:0] signals to

bank 1 on the FPGA.

• The LM-EP20K600E+ is fitted with an Altera FPGA and routes the interface

module ABANK[59:0] signals to bank 5 on the FPGA and the BBANK[53:0]

signals to bank 6 on the FGPA.

Note

These pin assignments are contained in the example pin constraints file on the CD

supplied with the interface module.

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ARM IM-AD1 Betriebsanweisung Seite 26