
LPC2141_42_44_46_48 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 12 August 2011 31 of 45
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
9.1 Timing
Fig 6. External clock timing (with an amplitude of at least V
i(RMS)
= 200 mV)
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
Fig 7. Differential data-to-EOP transition skew and EOP width
002aab561
T
PERIOD
differential
data lines
crossover point
source EOP width: t
FEOPT
receiver EOP width: t
EOPR1
, t
EOPR2
crossover point
extended
differential data to
SE0/EOP skew
n × T
PERIOD
+ t
FDEOP
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