ARM ARM7TDMI Bedienungsanleitung

Department of Electrical and Computer Engineering University of Wisconsin-Madison ECE 353/315 ARM7TDMI Instruction Set Reference M

Page 6 3.2.10 Register Operand, Rotate Right by Register The register value is rotated right by a value contained in a register. The C flag will be

Page 7 3.3.3 Base register with shifted register offset [Rn, +/-<Rm>, <shift> #<shift_immediate>] memory_address = Rn +/- shifted

Page 8 3.4 Miscellaneous Load/Store Addressing Modes These options apply only to the LDRSB, LDRH, LDRSH, STRH instructions. There are six options tha

Page 9 3.5 Memory Allocation and Operand Alignment This section presents an abridged list of the most commonly used assembler directives. Full docume

Page 10 numeric constants or program-relative expressions (i.e. labels). DCDU allocates without ensuring alignment. If DCDU is followed by a label tha

Page 11 3.6.4 ENTRY – Code Entry Point Syntax: ENTRY Description: The ENTRY directive indicates the point in the code where program execution should

Page 12 4 Instruction Descriptions 4.1 General Information A number of ARM7TDMI instructions will not be used in conjunction with the ADuC7026 proce

Page 13 4.3 ADD - Add Syntax: ADD{<cond>}{S} <Rd>, <Rn>, <shifter_operand> RTL: if(cond) Rd  Rn + shifter_operand Flags u

Page 14 4.5 B, BL – Branch, Branch and Link Syntax: B{<cond>} <target_address>, BL{<cond>} <target_address> RTL: if(cond) i

Page 15 4.6 BIC – Bit Clear Syntax: BIC{<cond>}{S} <Rd>, <Rn>, <shifter_operand> RTL: if(cond) Rd  Rn AND NOT shifter_oper

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Page 16 4.8 CMN – Compare Negative Syntax: CMN{<cond>} <Rn>, <shifter_operand> RTL: if(cond) Rn + shifter_operand Flags updated:

Page 17 4.10 EOR – Bit-wise Exclusive-OR Syntax: EOR{<cond>}{S} <Rd>, <Rn>, <shifter_operand> RTL: if(cond) Rd  Rn XOR shif

Page 18 Usage and Examples: The LDM instruction permits block moves of memory to the registers and enables efficient stack operations. The registers m

Page 19 The instructions below demonstrate a push operation followed by a pop operation assuming an empty-ascending stack. Note that by including the

Page 20 4.13 LDRB – Load Register Byte Syntax: LDRB{<cond>} <Rd>, <addressing_mode> RTL: if(cond) Rd[7:0]  memory[memory_address]

Page 21 4.15 LDRSB – Load Register Signed Byte Syntax: LDRSB{<cond>} <Rd>, <addressing_mode> RTL: if(cond) Rd[7:0]  memory[memory

Page 22 4.17 MLA – Multiply-Accumulate Syntax: MLA{<cond>}{S} <Rd >, <Rm>, <Rs>, <Rn> RTL: if(cond) Rd  Rn + (Rs • Rm

Page 23 4.19 MRS – Move PSR into General-Purpose Register Syntax: MRS{<cond>} <Rd >, CPSR MRS{<cond>} <Rd >, SPSR RTL: if(con

Page 24 The <fields> indicate which fields of the CPSR/SPSR be written to should be allowed to be changed. This limits any changes just to the f

Page 25 4.22 MVN – Move Negative Syntax: MVN{<cond>}{S} <Rd>, <shifter_operand> RTL: if(cond) Rd  NOT shifter_operand if(S==1 and

i Table of Contents 1 Instruction Encoding ...

Page 26 4.24 RSB – Reverse Subtract Syntax: RSB{<cond>}{S} <Rd>, <Rn>, <shifter_operand> RTL: if(cond) Rd  shifter_operand

Page 27 4.26 SBC – Subtract with Carry Syntax: SBC{<cond>}{S} <Rd>, <Rn>, <shifter_operand> RTL: if(cond) Rd  Rn - shifter_

Page 28 4.28 SMULL – Signed Multiply Long Syntax: SMULL{<cond>}{S} <Rd_LSW>, <Rd_MSW>, <Rm>, <Rs> RTL: if(cond) Rd_MSW

Page 29 Usage and Examples: The STM instruction permits block moves of registers to memory and enables efficient stack operations. The registers may b

Page 30 4.30 STR – Store Register Syntax: STR{<cond>} <Rd>, <addressing_mode> RTL: if(cond) memory[memory_address]  Rd if(writeb

Page 31 4.32 STRH – Store Register Halfword Syntax: STRH{<cond>} <Rd>, <addressing_mode> RTL: if(cond) memory[memory_address]  Rd

Page 32 4.34 SWI – Software Interrupt Syntax: SWI{<cond>} <immediate_24> RTL: if(cond) R14_svc  address of next instruction after SWI i

Page 33 Usage and Examples: The SWP instruction exchanges a word between a register and memory. This instruction is intended to support semaphore man

Page 34 4.37 TEQ – Test Equivalence Syntax: TEQ{<cond>} <Rn>, <shifter_operand> RTL: if(cond) Rn XOR shifter_operand Flags update

Page 35 4.39 UMLAL – Unsigned Multiply-Accumulate Long Syntax: UMLAL{<cond>}{S} <Rd_LSW>, <Rd_MSW>, <Rm>, <Rs> RTL: if(

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Page 36 5 Pseudo-Instructions 5.1 ADR – Load Address (short-range) Syntax: ADR{cond} <Rd>, <label> Description: The ADR pseudo-instruct

Page 37 5.4 LDR – Load Register Syntax: LDR{cond} <Rd>, =<expression> LDR{cond} <Rd>, =<label-expression> Description: The L

Page 38 5.7 NOP – No Operation Syntax: NOP Description: There are numerous ways to encode a NOP (no operation) instruction for the ARM7TDMI processo

Page 39 5.11 RRX – Rotate Right with Extend Syntax: RRX{cond}{S} <Rd>, <Rm> Description: RRX is a synonym for the MOV instruction with an

Page 1 1 Instruction Encoding 1.1 ARM7TDMI – ARM Instructions The ARM7TDMI uses a fixed-length, 32-bit instruction encoding scheme for all ARM instr

Page 2 1.2 ARM7TDMI – THUMB Instructions The ARM7TDMI uses a fixed-length, 16-bit instruction encoding scheme for all Thumb instructions. The Thumb i

Page 3 3 Addressing, Operands and Directives 3.1 General Notes In general, using R15 (PC) as the destination register is not appropriate for most in

Page 4 3.2.2 Register Operands The register value is used directly. The C flag is unchanged. Note that this is actually a form of the Register Opera

Page 5 3.2.6 Register Operand, Logical Shift Right by Register The register value is shifted right by a value contained in a register. The C flag wi